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The trigger divider (Clock divider) uses a 4024 Cmos chip
to divide the incoming clock pulses by 2,4,8 and 16. The
4024 has a reset input, and this is used of course too.
The schematic shows only the driver of output N/2, the
other outputs look similiar.
The digital noise is a well known design : just take
some shift registers and xor's, and you get a pseudorandom
signal. The repetition time is really long ! I plan to implement the
same with an atmel AVR controller, and it is also a good idea to feed
the output of the digital noise into an 8 step shift register
(serial to parallel) and use the 8 bits for D/A conversion. With
an exponential series of resistors for these 8 bits, the distribution of
the outcoming volatage will be equal (256 different voltages). With all
resistors having the same value, the distribution
of the outcoming volatage will be binomial, and there are only 9
different voltages (including 0 volt).
The following schematic represents an A-R-Envelope Generator.
If you just solder the Release-Input-Pot-and-diode, you get
a R-Envelope Generator.